CMOS & CMOS NAND Gate Circuit
CMOS stands for ‘Complementary Metal Oxide semiconductor’. CMOS consists of both N-channel and P-channel MOS transistors arranged in a ‘complementary’ connection. These circuits have very good noise immunity and very low power dissipation than that the TTL and hence these CMOS circuits are greatly used in pocket calculators, digital wrist watches and portable computers.
CMOS NAND Gate Circuit:
CMOS two-input NAND gate circuit is shown in the Fig. 3.6. In the circuit, the P-channel MOS transistor Qj. and N-channel MOS transistor Q form one complementary connection; and similarly Q and Q form another complementary connection.
Note that the transistors used in the circuit acts as switches. The switching operations of these transistors for LOW and HIGH inputs. In the circuit, the output is pulled up to the supply voltage (HIGH), when either Qj. or Q2 is conducting.
The output is pulled down to ground (LOW) only when Q and Q.j are conducting.
- operation of CMOS & NAND
- CMOS & CMOS NAND Gate Circuit
- TTD NAND Gate with open-collector outputs in Digital Electronics
- TTL NAND Gate with Totem Pole Outputs in Digital Electronics
- TTL Circuits in Digital Electronics
- Digital Logic Families in Digital Electronics
- Inverter Circuit in Digital Electronics
- Logic Ciircuits in Digital Electronics:
- Basic Logic Operations for Gate networks in Digital Electronics
- Introduction to Boolean Algebra in Digital Electronics